Hyper-Threaded Multiplier for HECC

Gabriel Gallin 1 Arnaud Tisserand 2
1 CAIRN - Energy Efficient Computing ArchItectures with Embedded Reconfigurable Resources
Inria Rennes – Bretagne Atlantique , IRISA_D3 - ARCHITECTURE
2 Lab-STICC_UBS_CACS_MOCS
Lab-STICC - Laboratoire des sciences et techniques de l'information, de la communication et de la connaissance
Abstract : Modular multiplication is the most costly and common operation in hyper-elliptic curve cryptography. Over prime fields, it uses dependent partial products and reduction steps. These dependencies make FPGA implementations with fully pipelined DSP blocks difficult to optimize. We propose a new multiplier architecture with hyper-threaded capabilities. Several independent multiplications are handled in parallel for efficiently filling the pipeline and overlapping internal latencies by independent computations. It increases the silicon efficiency and leads to a better area / computation time trade-off than current state of the art. We use this hyper-threaded multiplier into small accelerators for hyper-elliptic curve cryptography in embedded systems.
Type de document :
Communication dans un congrès
Asilomar Conference on Signals, Systems, and Computers, Oct 2017, Pacific Grove, CA, United States. IEEE, 2017, 〈http://www.asilomarsscconf.org/〉
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Contributeur : Arnaud Tisserand <>
Soumis le : vendredi 20 octobre 2017 - 10:00:24
Dernière modification le : vendredi 9 février 2018 - 15:40:02
Document(s) archivé(s) le : dimanche 21 janvier 2018 - 12:33:32

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  • HAL Id : hal-01620046, version 1

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Gabriel Gallin, Arnaud Tisserand. Hyper-Threaded Multiplier for HECC. Asilomar Conference on Signals, Systems, and Computers, Oct 2017, Pacific Grove, CA, United States. IEEE, 2017, 〈http://www.asilomarsscconf.org/〉. 〈hal-01620046〉

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