A Sub-nJ CMOS ECG Classifier for Wireless Smart Sensor

Paul Chollet (1, 2, 3) , Cyril Lahuec (1, 2, 3) , Matthieu Arzel (1, 2, 3) , Fabrice Seguin (1, 2, 3)

1 Lab-STICC_IMTA_CACS_IAS
2 IMT Atlantique - ELEC - Département Electronique
3 Lab-STICC - Laboratoire des sciences et techniques de l'information, de la communication et de la connaissance

Body area sensor networks hold the promise of more efficient and cheaper medical care services through the constant monitoring of physiological markers such as heart beats. Continuously transmitting the electrocardiogram (ECG) signal requires most of the wireless ECG sensor energy budget. This paper presents the analog implantation of a classifier for ECG signals that can be embedded onto a sensor. The classifier is a sparse neural associative memory. It is implemented using the ST 65 nm CMOS technology and requires only 234 pJ per classification while achieving a 93.6% classification accuracy. The energy requirement is 6 orders of magnitude lower than a digital accelerator that performs a similar task. The lifespan of the resulting sensor is 8 times as large as that of a sensor sending all the data.

Mots clés: ECG; Diagnosis system; CMOS analogue integrated circuits; Neural Networks

Domaines: Electronique; Traitement du signal et de l'image [eess.SP]; Cardiologie et système cardiovasculaire

Paul Chollet, Cyril Lahuec, Matthieu Arzel, Fabrice Seguin. A Sub-nJ CMOS ECG Classifier for Wireless Smart Sensor. EMBC 2017 : 39th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, Jul 2017, Jeju, South Korea. pp.3840 - 3843, ⟨10.1109/EMBC.2017.8037694⟩. ⟨hal-01616520⟩