Architecture level Optimizations for Kummer based HECC on FPGAs

Gabriel Gallin 1 Turku Ozlum Celik 2 Arnaud Tisserand 3
1 CAIRN - Energy Efficient Computing ArchItectures with Embedded Reconfigurable Resources
Inria Rennes – Bretagne Atlantique , IRISA_D3 - ARCHITECTURE
3 Lab-STICC_UBS_CACS_MOCS
Lab-STICC - Laboratoire des sciences et techniques de l'information, de la communication et de la connaissance
Abstract : On the basis of a software implementation of Kummer based HECC over Fp presented in 2016, we propose new hardware architectures. Our main objectives are: definition of architecture parameters (type, size and number of units for arithmetic operations, memory and internal communications); architecture style optimization to exploit internal par-allelism. Several architectures have been designed and implemented on FPGAs for scalar multiplication acceleration in embedded systems. Our results show significant area reduction for similar computation time than best state of the art hardware implementations of curve based solutions.
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Submitted on : Tuesday, October 10, 2017 - 2:02:32 PM
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Gabriel Gallin, Turku Ozlum Celik, Arnaud Tisserand. Architecture level Optimizations for Kummer based HECC on FPGAs. IndoCrypt 2017 - 18th International Conference on Cryptology in India, Dec 2017, Chennai, India. pp.44-64, ⟨10.1007/978-3-319-71667-1_3⟩. ⟨hal-01614063⟩

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