Hardware Error Correction using Local Syndromes

Mohamed Hafidhi 1 Emmanuel Boutillon 2
1 Lab-STICC_UBS_CACS_IAS
Lab-STICC - Laboratoire des sciences et techniques de l'information, de la communication et de la connaissance
2 Lab-STICC_UBS_CACS_IAS
Lab-STICC - Laboratoire des sciences et techniques de l'information, de la communication et de la connaissance
Abstract : Increasing the integration density offers the possibility for designers to built very complex system on a single chip. However, approaching the limits of integration, circuit reliability has emerged as a critical concern. The loss of reliability increases with process/voltage and temperature (PVT) variations. Faults can appear in circuits which can affect the system behaviour and lead to a system failure. Therefore it is increasingly important to build more fault tolerant resilient system. This paper proposes a new fault tolerant scheme, the Duplication with Syndrome based Correction (DSC) scheme. Two criteria were considered to evaluate the proposed scheme: the reliability (probability that no error appears in the output of the architecture) and the hardware efficiency of the architecture. Results show that the DSC scheme reduces the complexity by 32%, compared to the classical Triple Modular Redundancy (TMR) scheme, while maintaining a level of reliability closed to the TMR. The paper shows also an example of signal processing applications where the DSC has been used to protect the correlation function and filters inside the tracking loops of the Global Positioning System (GPS) receiver.
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Communication dans un congrès
IEEE International workshop on Signal Processing Systems (SIPS 2017), Oct 2017, Lorient, France. 〈https://sips2017.sciencesconf.org/〉
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Mohamed Hafidhi, Emmanuel Boutillon. Hardware Error Correction using Local Syndromes. IEEE International workshop on Signal Processing Systems (SIPS 2017), Oct 2017, Lorient, France. 〈https://sips2017.sciencesconf.org/〉. 〈hal-01611117〉

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