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Fast and Parallel AAC Decoder Architecture for a Digital Radio Mondiale 30 Receiver

Abstract : An embedded real-time indexing engine for live radio stations requires a high-speed parallel advanced audio coding (AAC) decoder architecture to decode hundreds of compressed audio streams broadcast in the digital radio mondiale band. Several AAC hardware core units must be integrated into a single chip and synchronized with a global controller to achieve such high performance. This paper proposes a new parallel AAC decoder architecture to address this challenge. The proposed architecture includes multiple AAC decoder core units, each of which achieves a speed-up by a factor of 2 compared with the existing AAC decoder core units while using optimal logic resources. The proposed architecture overcomes several challenges faced by existing architectures. The Huffman decoder module decodes one word per clock cycle regardless of word length, and a smaller lookup table size is achieved for the inverse quantization module. The inverse modified discrete cosine transform architecture is fully pipelined, and the resource sharing technique is used to reduce the logic area. An initial prototype is implemented on an FPGA platform.
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Submitted on : Friday, November 3, 2017 - 11:21:25 AM
Last modification on : Monday, January 25, 2021 - 3:16:04 PM
Long-term archiving on: : Sunday, February 4, 2018 - 1:07:02 PM

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Mohammed Shaaban Ibraheem, Khalil Hachicha, Olivier Romain. Fast and Parallel AAC Decoder Architecture for a Digital Radio Mondiale 30 Receiver. IEEE Access, IEEE, 2017, 5, pp.14638 - 14646. ⟨10.1109/ACCESS.2017.2731902⟩. ⟨hal-01596494⟩

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