An ultra-low power iterative clique-based neural network integrated in 65-nm CMOS - Archive ouverte HAL Accéder directement au contenu
Communication Dans Un Congrès Année : 2017

An ultra-low power iterative clique-based neural network integrated in 65-nm CMOS

Résumé

Clique-based neural networks are less complex than commonly used neural network models. They have a limited connectivity and are composed of simple functions. They are thus adapted to implement neuro-inspired computation units operating under severe energy constraints. This paper shows an ST 65-nm CMOS ASIC implementation for a 30-neuron cliquebased neural network circuit. With a 1V power supply and 300nA unitary current, the neuron energy consumption is only 17fJ per synaptic event. The network occupies 41,820um² silicon area.
Fichier non déposé

Dates et versions

hal-01596340 , version 1 (27-09-2017)

Identifiants

Citer

Paul Chollet, Benoit Larras, Cyril Lahuec, Fabrice Seguin, Matthieu Arzel. An ultra-low power iterative clique-based neural network integrated in 65-nm CMOS. NEWCAS 2017 : 15th IEEE International New Circuits and Systems Conference, Jun 2017, Strasbourg, France. pp.5 - 8, ⟨10.1109/NEWCAS.2017.8010091⟩. ⟨hal-01596340⟩
68 Consultations
0 Téléchargements

Altmetric

Partager

Gmail Facebook X LinkedIn More