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Synchronous 8-bit Non-Volatile Full-Adder based on Spin Transfer Torque Magnetic Tunnel Junction

Abstract : With the continuous shrinking of technology node, conventional CMOS logic circuits suffer from high power issues due to both increasing leakage current and long traffic delay. Hybrid non-volatile (NV) logic-in-memory architecture, where emerging NV memories are distributed over a logic-circuit plane, has been widely investigated to overcome these limitations. Magnetic tunnel junction (MTJ) is considered as one of the most promising NV candidates thanks to its non-volatility, fast access speed, infinite endurance and easy 3-D integration with CMOS technology. Recently, several 1-bit NV full-adder (FA) structures using MTJ have been proposed to build low-power high-density arithmetic/logic unit for processors. However, one of their major disadvantages is partial non-volatility since they only use MTJs as one of their operands. For the purpose of extending 1-bit NV-FA to multi-bit structure and realizing full non-volatility, synchronous 8-bit NV-FA architecture is presented in this paper, where all the input signals are stored in MTJs instead of CMOS registers. Three possible structures are proposed with respect to different locations of NV data. By using an industrial CMOS 28 nm design kit and a MTJ compact model, we validated their functionalities and compared their performances in terms of power consumption and area, etc.
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Contributor : Jérôme Planès <>
Submitted on : Tuesday, September 19, 2017 - 9:39:55 AM
Last modification on : Tuesday, December 8, 2020 - 10:32:13 AM




Erya Deng, Yue Zhang, Wang Kang, Bernard Dieny, Jacques-Olivier Klein, et al.. Synchronous 8-bit Non-Volatile Full-Adder based on Spin Transfer Torque Magnetic Tunnel Junction. IEEE Transactions on Circuits and Systems I: Regular Papers, IEEE, 2015, 62 (7), pp.1757-1765. ⟨10.1109/tcsi.2015.2423751⟩. ⟨hal-01589783⟩



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