Efficiency modeling and exploration of 64-bit ARM compute nodes for exascale

Joël Wanza Weloli (1, 2) , Sébastien Bilavarn (2) , Martin de Vries (1) , Said Derradji (1) , Cécile Belleudy (2)

1 Bull atos technologies
2 LEAT - Laboratoire d'Electronique, Antennes et Télécommunications

This paper investigates the use of 64-bit ARM cores to improve the processing efficiency of upcoming HPC systems. It describes a set of available tools, models and platforms, and their combination in an efficient methodology for the design space exploration of large manycore computing clusters. Experimentations and results using representative benchmarks allow to set an exploration approach to evaluate essential design options at micro-architectural level while scaling with a large number of cores. We then apply this methodology to examine the validity of SoC partitioning as an alternative to using large SoC designs based on coherent multi-SoC models and the proposed SoC Coherent Interconnect (SCI).

Domaines: Systèmes embarqués; Architectures Matérielles [cs.AR]

Joël Wanza Weloli, Sébastien Bilavarn, Martin de Vries, Said Derradji, Cécile Belleudy. Efficiency modeling and exploration of 64-bit ARM compute nodes for exascale. Microprocessors and Microsystems: Embedded Hardware Design , 2017, 53, pp.68 - 80. ⟨10.1016/j.micpro.2017.06.019⟩. ⟨hal-01586191v2⟩