R. Wilhelm and J. Reineke, Embedded systems: Many cores — Many problems, 7th IEEE International Symposium on Industrial Embedded Systems (SIES'12), pp.176-180, 2012.
DOI : 10.1109/SIES.2012.6356583

E. Betti, S. Bak, R. Pellizzoni, M. Caccamo, and L. Sha, Real-Time I/O Management System with COTS Peripherals, IEEE Transactions on Computers, vol.62, issue.1, pp.45-58, 2013.
DOI : 10.1109/TC.2011.202

A. Abel, F. Benz, J. Doerfert, B. Dörr, S. Hahn et al., Impact of Resource Sharing on Performance and Performance Prediction: A Survey, 24th International Conference on Concurrency Theory (CONCUR'13), pp.25-43, 2013.
DOI : 10.1007/978-3-642-40184-8_3

. Kalray, The MPPA hardware architecture, 2012.

C. Ekelin, An Optimization Framework for Scheduling of Embedded Real-Time Systems, CPLEX Optimization Studio, 2004.

W. Puffitsch, ´. E. Noulard, and C. Pagetti, Off-line mapping of multi-rate dependent task sets to many-core platforms, Real-Time Systems, vol.19, issue.2, pp.526-565, 2015.
DOI : 10.1109/32.214831

B. Absint-angewandte-informatik-gmbh, D. De-dinechin, M. Van-amstel, G. Poulhies, ´. E. Lager et al., Timecritical computing on a single-chip massively parallel processor A General Theory for Deadlock Avoidance in Wormhole-Routed Networks, 18th Design, Automation & Test in Europe Conference and Exhibition (DATE'14), 2014, pp.1-6, 1998.

Q. Perret, P. Maurère, ´. E. Noulard, C. Pagetti, P. Sainrat et al., Predictable composition of memory accesses on many-core processors, 8th Conference on Embedded Real Time Software and Systems (ERTS'16), 2016.
URL : https://hal.archives-ouvertes.fr/hal-01256000

J. Nowotsch and M. Paulitsch, Leveraging Multi-core Computing Architectures in Avionics, 2012 Ninth European Dependable Computing Conference, pp.132-143, 2012.
DOI : 10.1109/EDCC.2012.27

J. Bin, S. Girbal, D. G. Prez, A. Grasset, and A. Merigot, Studying co-running avionic real-time applications on multi-core COTS architectures, 7th Conference on Embedded Real Time Software and Systems (ERTS'14), 2014.

C. Pagetti, D. Saussie, R. Gratia, ´. E. Noulard, and P. Siron, The ROSACE case study: From Simulink specification to multi/many-core execution, 2014 IEEE 19th Real-Time and Embedded Technology and Applications Symposium (RTAS), pp.309-318, 2014.
DOI : 10.1109/RTAS.2014.6926012

S. Chattopadhyay, A. Roychoudhury, and T. Mitra, Modeling shared cache and bus in multi-cores for timing analysis, Proceedings of the 13th International Workshop on Software & Compilers for Embedded Systems, SCOPES '10, pp.1-10, 2010.
DOI : 10.1145/1811212.1811220

R. Pellizzoni, E. Betti, S. Bak, G. Yao, J. Criswell et al., A Predictable Execution Model for COTS-Based Embedded Systems, 2011 17th IEEE Real-Time and Embedded Technology and Applications Symposium, pp.269-279, 2011.
DOI : 10.1109/RTAS.2011.33

]. F. Boniol, H. Cassé, ´. E. Noulard, and C. Pagetti, Deterministic Execution Model on COTS Hardware, 25th International Conference on Architecture of Computing Systems (ARCS'12), pp.98-110, 2012.
DOI : 10.1145/1347375.1347389

G. Durrieu, M. Faugère, S. Girbal, D. Gracia-pérez, C. Pagetti et al., Predictable Flight Management System Implementation on a Multicore Processor, 7th Conference on Embedded Real Time Software and Systems (ERTS'14), 2014.
URL : https://hal.archives-ouvertes.fr/hal-01121700

H. Yun, G. Yao, R. Pellizzoni, M. Caccamo, and L. Sha, Mem- Guard: Memory bandwidth reservation system for efficient performance isolation in multi-core platforms, 19th Real-Time and Embedded Technology and Applications Symposium (RTAS'13), pp.55-64, 2013.

J. Nowotsch, M. Paulitsch, D. Bühler, H. Theiling, S. Wegener et al., Multi-core Interference-Sensitive WCET Analysis Leveraging Runtime Resource Capacity Enforcement, 2014 26th Euromicro Conference on Real-Time Systems, pp.109-118, 2014.
DOI : 10.1109/ECRTS.2014.20
URL : http://opus.bibliothek.uni-augsburg.de/opus4/files/2474/TR_2013_10.pdf

X. Jean, D. Faura, M. Gatti, L. Pautet, and T. Robert, Ensuring robust partitioning in multicore platforms for IMA systems, 2012 IEEE/AIAA 31st Digital Avionics Systems Conference (DASC), pp.7-11, 2012.
DOI : 10.1109/DASC.2012.6382408

S. Girbal, X. Jean, J. Le-rhun, D. G. Prez, and M. Gatti, Deterministic Platform Software for Hard Real-Time systems using multi-core COTS, 34th Digital Avionics Systems Conference (DASC'15), 2015.
DOI : 10.1109/dasc.2015.7311481
URL : https://zenodo.org/record/57261/files/2015DASC-TRT.2.pdf

T. Carle, M. Djemal, D. Potop-butucaru, and R. Simone, Static Mapping of Real-Time Applications onto Massively Parallel Processor Arrays, 2014 14th International Conference on Application of Concurrency to System Design, pp.112-121, 2014.
DOI : 10.1109/ACSD.2014.19
URL : https://hal.archives-ouvertes.fr/hal-01095130

S. S. Craciunas and R. S. Oliver, SMT-based Task- and Network-level Static Schedule Generation for Time-Triggered Networked Systems, Proceedings of the 22nd International Conference on Real-Time Networks and Systems, RTNS '14, pp.4545-4554, 2014.
DOI : 10.1145/2659787.2659812

R. Gorcitz, E. Kofman, T. Carle, D. Potop-butucaru, and R. Simone, On the Scalability of Constraint Solving for Static/Off-Line Real-Time Scheduling, 13th International Conference on Formal Modeling and Analysis of Timed Systems (FORMATS'15), pp.108-123, 2015.
DOI : 10.1007/978-3-319-22975-1_8
URL : https://hal.archives-ouvertes.fr/hal-01179489

B. Doud, Accelerating the Data Plane With the TILE-Mx Manycore Processor, Linley Data Center Conference, 2015.

J. Boudec and P. Thiran, Network Calculus: A Theory of Deterministic Queuing Systems for the Internet, 2001.

R. Cruz, A calculus for network delay. I. Network elements in isolation, IEEE Transactions on Information Theory, vol.37, issue.1, pp.114-131, 1991.
DOI : 10.1109/18.61109

L. Thiele, S. Chakraborty, and M. Naedele, Real-time calculus for scheduling hard real-time systems, 2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353), pp.101-104, 2000.
DOI : 10.1109/ISCAS.2000.858698

Y. Qian, Z. Lu, and W. Dou, Analysis of Worst-Case Delay Bounds for On-Chip Packet-Switching Networks, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.29, issue.5, pp.802-815, 2010.
DOI : 10.1109/TCAD.2010.2043572

G. Giannopoulou, N. Stoimenov, P. Huang, L. Thiele, and B. D. De-dinechin, Mixed-criticality scheduling on cluster-based manycores with shared communication and storage resources Real-Time Systems, pp.1-51, 2015.
DOI : 10.1007/s11241-015-9227-y

S. Hahn, J. Reineke, and R. Wilhelm, Towards compositionality in execution time analysis, ACM SIGBED Review, vol.12, issue.1, pp.28-36, 2015.
DOI : 10.1109/TCAD.2009.2013287

E. Kasapaki and J. Spars, Argo: A Time-Elastic Time-Division-Multiplexed NOC Using Asynchronous Routers, 2014 20th IEEE International Symposium on Asynchronous Circuits and Systems, pp.45-52, 2014.
DOI : 10.1109/ASYNC.2014.14

K. Goossens, J. Dielissen, and A. Radulescu, ??thereal Network on Chip:Concepts, Architectures, and Implementations, IEEE Design and Test of Computers, vol.22, issue.5, pp.414-421, 2005.
DOI : 10.1109/MDT.2005.99

M. Ziccardi, A. Cornaglia, E. Mezzetti, and T. Vardanega, Softwareenforced Interconnect Arbitration for COTS Multicores, 15th International Workshop on Worst-Case Execution Time Analysis (WCET'15), pp.11-20, 2015.

M. Paolieri, E. Quiones, F. Cazorla, and M. Valero, An Analyzable Memory Controller for Hard Real-Time CMPs, IEEE Embedded Systems Letters, vol.1, issue.4, pp.86-90, 2009.
DOI : 10.1109/LES.2010.2041634
URL : http://upcommons.upc.edu/bitstream/2117/7462/1/An%20analyzable%20memory%20controller%20....pdf

B. Akesson, K. Goossens, and M. Ringhofer, Predator, Proceedings of the 5th IEEE/ACM international conference on Hardware/software codesign and system synthesis , CODES+ISSS '07, pp.251-256, 2007.
DOI : 10.1145/1289816.1289877

J. Reineke, I. Liu, H. D. Patel, S. Kim, and E. A. Lee, PRET DRAM controller, Proceedings of the seventh IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis, CODES+ISSS '11, pp.99-108, 2011.
DOI : 10.1145/2039370.2039388

Y. Krishnapillai, Z. P. Wu, and R. Pellizzoni, A Rank-Switching, Open-Row DRAM Controller for Time-Predictable Systems, 2014 26th Euromicro Conference on Real-Time Systems, pp.27-38, 2014.
DOI : 10.1109/ECRTS.2014.37

H. Kim, D. De-niz, B. Andersson, M. Klein, O. Mutlu et al., Bounding memory interference delay in COTS-based multi-core systems, 2014 IEEE 19th Real-Time and Embedded Technology and Applications Symposium (RTAS), pp.145-154, 2014.
DOI : 10.1109/RTAS.2014.6925998
URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.646.316

H. Yun, R. Pellizzoni, and P. K. Valsan, Parallelism-Aware Memory Interference Delay Analysis for COTS Multicore Systems, 2015 27th Euromicro Conference on Real-Time Systems, pp.184-195, 2015.
DOI : 10.1109/ECRTS.2015.24
URL : http://arxiv.org/pdf/1407.7448

Z. P. Wu, Y. Krish, and R. Pellizzoni, Worst Case Analysis of DRAM Latency in Multi-requestor Systems, 2013 IEEE 34th Real-Time Systems Symposium, pp.372-383, 2013.
DOI : 10.1109/RTSS.2013.44

R. Pellizzoni, A. Schranzhofer, J. Chen, M. Caccamo, and L. Thiele, Worst case delay analysis for memory interference in multicore systems, 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010), pp.741-746, 2010.
DOI : 10.1109/DATE.2010.5456952

G. Yao, R. Pellizzoni, S. Bak, H. Yun, and M. Caccamo, Global Real-Time Memory-Centric Scheduling for Multicore Systems, IEEE Transactions on Computers, vol.65, issue.9
DOI : 10.1109/TC.2015.2500572

G. Yao, R. Pellizzoni, S. Bak, E. Betti, and M. Caccamo, Memory-centric scheduling for multicore hard real-time systems, Real-Time Systems, vol.29, issue.5, pp.681-715, 2012.
DOI : 10.1109/RTAS.2010.24