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Communication Dans Un Congrès Année : 2000

CAS-BUS: A Scalable and Reconfigurable Test Access Mechanism for Systems on a Chip

Résumé

This paper describes CAS-BUS, a P1500 compatible test access mechanism for systems on a chip. The TAM architecture is made up of a core access switch (CAS) and a test bus. The TAM characteristics are its flexibility, scalability and reconfigurability. A CAS generator has been developed, and some results are provided in the paper.
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Dates et versions

hal-01573606 , version 1 (10-08-2017)

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Mounir Benabdenbi, Walid Maroufi, Meryem Marzouki. CAS-BUS: A Scalable and Reconfigurable Test Access Mechanism for Systems on a Chip. Design Automation and Test in Europe Conference (DATE'2000), Mar 2000, Paris, France. pp.141-145, ⟨10.1109/DATE.2000.840030⟩. ⟨hal-01573606⟩
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