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Timed simulation of VLSI circuits using a FPGA net

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Conference papers
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https://hal.archives-ouvertes.fr/hal-01573065
Contributor : Lip6 Publications <>
Submitted on : Tuesday, August 8, 2017 - 2:20:53 PM
Last modification on : Thursday, March 21, 2019 - 1:09:51 PM

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  • HAL Id : hal-01573065, version 1

Citation

Laurent Vuillemin, Pirouz Bazargan Sabet. Timed simulation of VLSI circuits using a FPGA net. Applied Informatics (IASTED AI 2000), May 2000, Innsbruck, Austria. ⟨hal-01573065⟩

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