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GSM EFR Vocoder on a Configurable DSP Core, A Quantitative Analysis

Yann Bajot 1 Habib Mehrez 1 
1 ASIM - Architecture des Systèmes intégrés et Micro électronique
LIP6 - Laboratoire d'Informatique de Paris 6
Abstract : This paper deals with the implementation of the GSM EFR vocoder on a configurable DSP processor. We first present the highly configurable and modular architecture used in the model of our DSP core. Next, a quantitative analysis of the EFR algorithm regarding Instruction-Level Parallelism and Algorithm/Architecture Adequation is performed. This leads to define a cost-effective and powerful architecture with special features enabling an optimized implementation of the vocoder. The results obtained are shown and compared to those of state-of-art DSP Processors.
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Submitted on : Monday, August 7, 2017 - 5:50:09 PM
Last modification on : Sunday, June 26, 2022 - 9:42:49 AM


  • HAL Id : hal-01572597, version 1


Yann Bajot, Habib Mehrez. GSM EFR Vocoder on a Configurable DSP Core, A Quantitative Analysis. International Conference On Signal Processing Applications and Technologies (ICSPAT 2000), Oct 2000, Dallas, Texas, United States. pp.1-6. ⟨hal-01572597⟩



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