Hardware Architectures Exploration for Hyper-Elliptic Curve Cryptography

Gabriel Gallin 1 Arnaud Tisserand 2
1 CAIRN - Energy Efficient Computing ArchItectures with Embedded Reconfigurable Resources
Inria Rennes – Bretagne Atlantique , IRISA_D3 - ARCHITECTURE
Lab-STICC - Laboratoire des sciences et techniques de l'information, de la communication et de la connaissance
Abstract : Our research group has been studying arithmetic operators and implementations of hardware accelerators for ECC, with robustness against physical attacks such as Side Channel Analysis (SCA) or faults injections. We are now designing hardware accelerators for HECC scalar multiplication by exploring different types of architectures. We developed a specific CABA (Cycle Accurate, Bit Accurate) simulator for our architectures. With this simulator, we can study the impact of the type, number and size of the arithmetic units and of the choice between different types of parallel architecture on the performances, circuit area and resistance against physical attacks. We will also compare different ways to manage internal data transfers and different control flow implementations. The most interesting configurations will be implemented on FPGA and evaluated on our attack setup.
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Contributor : Arnaud Tisserand <>
Submitted on : Monday, June 26, 2017 - 5:29:47 PM
Last modification on : Wednesday, December 19, 2018 - 3:26:08 PM
Long-term archiving on : Wednesday, January 17, 2018 - 4:29:01 PM


  • HAL Id : hal-01547034, version 1


Gabriel Gallin, Arnaud Tisserand. Hardware Architectures Exploration for Hyper-Elliptic Curve Cryptography. Crypto'Puces 2017- 6ème rencontre Crypto'Puces, du composant au système communicant embarqué, May 2017, Porquerolles, France. pp.31. ⟨hal-01547034⟩



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