Hardware Architectures for HECC

Gabriel Gallin 1 Arnaud Tisserand 2
1 CAIRN - Energy Efficient Computing ArchItectures with Embedded Reconfigurable Resources
Inria Rennes – Bretagne Atlantique , IRISA_D3 - ARCHITECTURE
2 Lab-STICC_UBS_CACS_MOCS
Lab-STICC - Laboratoire des sciences et techniques de l'information, de la communication et de la connaissance
Abstract : Recent research has pointed out Hyper-Elliptic Curve Cryptography (HECC) as an attractive alternative to ECC in public-key cryptography. HECC is based on a different kind of curves, which allows the size of the field elements to be halved, but at the expense of an increased number of finite field operations. HECC internal parallelism brings forward numerous questions for hardware implementation. In this work, we present arithmetic operators and implementations of hardware accelerators for HECC. We first improved the hardware utilization of the multiplier unit with new solution named hyper-threaded modular multiplier which fills the unused stages of the DSP blocks with other independent modular multiplications. Then, we explore various architectures for our HECC accelerator, starting from a classical Harvard architecture and changing architectural parameters, such as the numbers and types of arithmetic units.
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Submitted on : Thursday, June 22, 2017 - 6:45:14 PM
Last modification on : Wednesday, December 19, 2018 - 3:26:08 PM
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  • HAL Id : hal-01545625, version 1

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Gabriel Gallin, Arnaud Tisserand. Hardware Architectures for HECC. CryptArchi 2017: 15th International Workshops on Cryptographic architectures embedded in logic devices , Jun 2017, Smolenice, Slovakia. ⟨hal-01545625⟩

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