Architectural performance analysis of FPGA synthesized LEON processors

Abstract : Current processors have gone through multiple internal opti- mization to speed-up the average execution time e.g. pipelines, branch prediction. Besides, internal communication mechanisms and shared resources like caches or buses have a sig- nificant impact on Worst-Case Execution Times (WCETs). Having an accurate estimate of a WCET is now a challenge. Probabilistic approaches provide a viable alternative to single WCET estimation. They consider WCET as a probabilistic distribution associated to uncertainty or risk. In this paper, we present synthetic benchmarks and associated analysis for several LEON3 configurations on FPGA targets. Benchmarking exposes key parameters to execution time variability allowing for accurate probabilistic modeling of system dynamics. We analyze the impact of architecture- level configurations on average and worst-case behaviors.
Keywords : FPGA WCET
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Corentin Damman, Gregory Edison, Fabrice Guet, Eric Noulard, Luca Santinelli, et al.. Architectural performance analysis of FPGA synthesized LEON processors. 27th International Symposium on Rapid System Prototyping, Oct 2016, Pittsburgh, United States. pp. 33-40, ⟨10.1145/2990299.2990306⟩. ⟨hal-01543282⟩

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