Fast SRAM-FPGA Fault Injection Platform based On Dynamic Partial Reconfiguration
Résumé
SRAM-based FPGAs are very sensitive to harsh conditions, like radiations or ionizations, and need to be hardened to insure correct running. To validate any fault tolerant solution for these SRAM-FPGA, fault injection campaigns must be conducted carefully. In this work, we present a new design flow to perform localized internal fault injection on specific parts of a Design Under Test (DUT). To achieve this, we combine between Partial Dynamic Reconfiguration (PDR) via Internal Configuration Access Port (ICAP) for rapid fault insertion on SRAM; Isolation Design Flow (IDF) to isolate both of placement and routing of Design Under Test into a specific partial region. Moreover, we applied realistic fault distribution laws deduced from ground-based radiation experiments to reflect realistic behavior of FPGA toward radiations. The implemented injection platform using this flow shows the importance of using distribution laws driven approach. Results show that our fault injection experiments are done more than 15 times faster than one of the traditional FPGA based fault injection methods with a speed-up on simulation time up to 8.