Mitigating Read & Write Errors in STT-MRAM Memories under DVS

Elena Ioana Vatajelu (1) , Rosa Rodríguez-Montañés (2) , Michel Renovell (3) , Joan Figueras (2)

1 TIMA - Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés
2 UPC - Universitat Politècnica de Catalunya = Université polytechnique de Catalogne [Barcelona]
3 TEST - Test and dEpendability of microelectronic integrated SysTems

In this paper we propose a methodology for reliability evaluation, failure prediction, and failure mitigation of a STT-MRAM memory under different supply voltage conditions (i.e., DVS scenarios). The methodology is based on the design of read/write failure predictor registers which are able to predict the memory failure probability for a given DVS scenario. The predicted results are used to re-tune the supply voltage such that the memory reliability is assured.

Domaines: Micro et nanotechnologies/Microélectronique

Elena Ioana Vatajelu, Rosa Rodríguez-Montañés, Michel Renovell, Joan Figueras. Mitigating Read & Write Errors in STT-MRAM Memories under DVS. ETS: European Test Symposium, May 2017, Limassol, Cyprus. ⟨10.1109/ETS.2017.7968209⟩. ⟨hal-01525720⟩