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Mitigating Read & Write Errors in STT-MRAM Memories under DVS

Abstract : In this paper we propose a methodology for reliability evaluation, failure prediction, and failure mitigation of a STT-MRAM memory under different supply voltage conditions (i.e., DVS scenarios). The methodology is based on the design of read/write failure predictor registers which are able to predict the memory failure probability for a given DVS scenario. The predicted results are used to re-tune the supply voltage such that the memory reliability is assured.
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Submitted on : Monday, May 22, 2017 - 10:39:59 AM
Last modification on : Friday, November 20, 2020 - 1:04:03 PM




Elena Ioana Vatajelu, Rosa Rodríguez-Montañés, Michel Renovell, Joan Figueras. Mitigating Read & Write Errors in STT-MRAM Memories under DVS. ETS: European Test Symposium, May 2017, Limassol, Cyprus. ⟨10.1109/ETS.2017.7968209⟩. ⟨hal-01525720⟩



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