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Automatic Layout of Scalable Embedded Field Programmable Gate Array

Abstract : This paper presents a layout technique for scalable embedded Field Programmable Gate Array architecture (eFPGA). It describes the total ?ow to generate a variety of eFPGA architectures using parameterized generators and Alliance CAD developed in the university of Paris6 We will show one example of realization using a symbolic library of cells. Our test eFPGA have a symmetric mesh architecture (Island-style) composed of ?ve main tiles. The scalability of this tiles can be varied to obtain the best design ?t on the System on Chip device.
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Submitted on : Thursday, May 11, 2017 - 2:45:22 PM
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Hayder Mrabet, Zied Marrakchi, Habib Mehrez, André Tissot. Automatic Layout of Scalable Embedded Field Programmable Gate Array. ICEEC 2004 - International Conference on Electrical Electronic and Computer Engineering, Sep 2004, Cairo, Egypt. pp.469-472, ⟨10.1109/ICEEC.2004.1374502⟩. ⟨hal-01521128⟩



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