High level synthesis methodology from C to FPGA used for a network protocol communication.

Abstract : This paper presents a "Kahn process network" methodology based on the DISYDENT platform (digital system design environment). The system is described by a set of communicating Kahn processes. This processes are C POSIX threads representing both software and hardware tasks. Each thread communicates with the others using channel-read / channel-write primitives. Thus, the system can be validated efficiently and quickly by software. System 's realization consists of synthesizing hardware tasks to RTL-VHDL language. This step is automated from C task to FPGA mapping. This paper shows the method's effectiveness through the realization of a network controller on FPGA enabling communication between two Linux stations.
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Conference papers
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https://hal.archives-ouvertes.fr/hal-01521121
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Submitted on : Thursday, May 11, 2017 - 2:39:43 PM
Last modification on : Thursday, March 21, 2019 - 2:31:48 PM

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Mouhamadou Diaby, Matthieu Tuna, Jean-Lou Desbarbieux, Franck Wajsbürt. High level synthesis methodology from C to FPGA used for a network protocol communication.. RSP 2004 - 15th International Workshop on Rapid System Prototyping, Jun 2004, Geneva, Switzerland. pp.103-108, ⟨10.1109/IWRSP.2004.1311103⟩. ⟨hal-01521121⟩

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