STEPS: experimenting a new software-based strategy for testing SoCs containing P1500-compliant IP cores

Abstract : This paper presents STEPS, an innovative software-based approach for testing P1500-compliant SoCs. STEPS is based on the concept that the ATE is not considered as an initiator applying vectors to the SoC test pins but rather as a target, a huge repository of 32-bits test data and control commands. The ATE is connected to the functional SoC external RAM controller interface. The only additional test component in the SoC is a P1500 test processor that converts test data into serial P1500 streams. This paper applies the STEPS methodology to SoCs containing a VCI-compliant interconnect, a microprocessor, P1500-compliant IP cores and an external RAM controller interface. Using the ITC02 SoC benchmarks, a comparison is done between the STEPS architecture and a classical bus-based strategy.
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Conference papers
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https://hal.archives-ouvertes.fr/hal-01521098
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Submitted on : Thursday, May 11, 2017 - 2:22:46 PM
Last modification on : Thursday, March 21, 2019 - 2:31:43 PM

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Mounir Benabdenbi, Alain Greiner, François Pêcheux, Emmanuel Viaud, Matthieu Tuna. STEPS: experimenting a new software-based strategy for testing SoCs containing P1500-compliant IP cores. DATE 2004 - Design Automation and Test in Europe Conference, Feb 2004, Paris, France. pp.712-713, ⟨10.1109/DATE.2004.1268943⟩. ⟨hal-01521098⟩

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