. Abdelouahab, . Bourrasset, . Pelcat, . Berry, and Q. Serot, A Holistic Approach for Optimizing DSP Block Utilization of a CNN implementation on FPGA, Proceedings of the 10th International Conference on Distributed Smart Camera, ICDSC '16, 2016.
DOI : 10.1145/2967413.2967430
URL : https://hal.archives-ouvertes.fr/hal-01415955

. Altera, Implementing Multipliers in FPGA Devices, Application Note, 2004.

A. Canziani, A. Paszke, and E. Culurciello, An Analysis of Deep Neural Network Models for Practical Applications, 2016.

S. Chakradhar, M. Sankaradas, V. Jakkula, and S. Cadambi, A Dynamically Conngurable Coprocessor for Convolutional Neural Networks
DOI : 10.1145/1816038.1815993

J. Cong and B. Xiao, Minimizing Computation in Convolutional Neural Networks, International Conference on Artiicial Neural Networks, pp.281-290, 2014.
DOI : 10.1007/978-3-319-11179-7_36

J. Deng, W. Dong, and R. Socher, Imagenet: A large-scale hierarchical image database, CVPR 2009. IEEE Conference

B. Jack, . Dennis, P. David, and . Misunas, A Preliminary Architecture for a Basic Data--ow Processor. ISCA '75

C. Farabet, Y. Lecun, E. Culurciello, and B. Martini, NeuFlow: A runtime reconngurable dataaow processor for vision, CVPRW'11
DOI : 10.1109/cvprw.2011.5981829
URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.228.9047

C. Farabet, C. Poulet, J. Han, and Y. Lecun, CNP: An FPGA-based processor for Convolutional Networks, 2009 International Conference on Field Programmable Logic and Applications, 2009.
DOI : 10.1109/FPL.2009.5272559
URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.419.9101

C. Farabet, C. Poulet, and Y. Lecun, An FPGA-Based Stream Processor for Embedded Real-Time Vision with CNNs, 2009.
DOI : 10.1109/iccvw.2009.5457611

H. Huttunen, F. Shokrollahi-yancheshmeh, and C. Ke, Car type recognition with Deep Neural Networks, 2016 IEEE Intelligent Vehicles Symposium (IV), 1115.
DOI : 10.1109/IVS.2016.7535529
URL : http://arxiv.org/abs/1602.07125

Y. Jia and E. Shelhamer, Caae: Convolutional Architecture for Fast Feature Embedding, ACM International Conference on Multimedia, 2014.

Y. Lecun, Y. Bottou, and . Bengio, Gradient-based learning applied to document recognition, Proceedings of the IEEE, 1998.
DOI : 10.1109/5.726791
URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.138.1115

M. Motamedi and P. Gysel, Design space exploration of FPGA-based Deep CNNs, 2016 (ASP-DAC)

K. Ovtcharov and O. Ruwase, Accelerating Deep Convolutional Neural Networks Using Specialized Hardware, 2015.

M. Peemen, . Setio, and . Mesman, Memory-centric accelerator design for Convolutional Neural Networks, 2013 IEEE 31st International Conference on Computer Design (ICCD), 2013.
DOI : 10.1109/ICCD.2013.6657019
URL : https://pure.tue.nl/ws/files/3997958/580711006684801.pdf

J. Sérot and F. Berry, High-Level Dataaow Programming for Reconngurable Computing, Computer Architecture and High Performance Computing Workshop, 2014.

G. Richard and . Shoup, Parameterized convolution ltering in a eld programmable gate array, Oxford, United Kingdom: Abingdon EE&CS Books. Citeseer, 1994.

K. Simonyan and A. Zisserman, Very deep convolutional networks for large-scale image recognition. arXiv preprint, pp.1-14, 2014.

C. Zhang, P. Li, G. Sun, Y. Guan, B. Xiao et al., Optimizing FPGAbased Accelerator Design for Deep Convolutional Neural Networks, Proceedings of the 2015
DOI : 10.1145/2684746.2689060