Assessing the Performance of the SRR Loop Scheduler with Irregular Workloads

Abstract : The power consumption of the High Performance Computing (HPC) systems is an increasing concern as large-scale systems grow in size and, consequently, consume more energy. In response to this challenge, we have develop and evaluate new energy-aware load balancers to reduce the average power demand and save energy of parallel systems when scientific applications with imbalanced load are executed. Our load balancers combine dynamic load balancing with DVFS techniques in order to reduce the clock frequency of underloaded computing cores which experience some residual imbalance even after tasks are remapped. The results show that our load balancers present power reductions of 7.5% in average with the fine-grained variant that performs per-core DVFS, and of 18.75% with the coarse-grained variant that performs per-chip DVFS over real applications.
Complete list of metadatas

Cited literature [13 references]  Display  Hide  Download
Contributor : Jean-Francois Méhaut <>
Submitted on : Saturday, May 6, 2017 - 12:21:14 PM
Last modification on : Monday, July 8, 2019 - 3:09:20 PM
Long-term archiving on : Monday, August 7, 2017 - 12:22:37 PM


Files produced by the author(s)


  • HAL Id : hal-01519205, version 1


Pedro Henrique Penna, Eduardo Inacio, Márcio Castro, Patrícia Plentz, Henrique Cota de Freitas, et al.. Assessing the Performance of the SRR Loop Scheduler with Irregular Workloads. International Conference on Computational Science (ICCS'17), Petros Koumoutsakos, Eleni Chatzi, Jun 2017, Zurich, Switzerland. ⟨hal-01519205⟩



Record views


Files downloads