More accurate complex multiplication for embedded processors

Claude-Pierre Jeannerod 1 Christophe Monat 2 Laurent Thévenoux 1
1 ARIC - Arithmetic and Computing
Inria Grenoble - Rhône-Alpes, LIP - Laboratoire de l'Informatique du Parallélisme
Abstract : This paper presents some work in progress on the development of fast and accurate support for complex floating-point arithmetic on embedded processors. Focusing on the case of multiplication, we describe algorithms and implementations for computing both the real and imaginary parts with high relative accuracy. We show that, in practice, such accuracy guarantees can be achieved with reasonable overhead compared with conventional algorithms (which are those offered by current implementations and for which the real or imaginary part of a product can have no correct digit at all). For example, the average execution-time overheads when computing an FFT on the ARM Cortex-A53 and -A57 processors range from 1.04x to 1.17x only, while arithmetic costs suggest overheads from 1.5x to 1.8x.
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Communication dans un congrès
12th IEEE International Symposium on Industrial Embedded Systems (SIES 2017), Jun 2017, Toulouse, France. <https://sies2017.org/>
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https://hal.archives-ouvertes.fr/hal-01512760
Contributeur : Laurent Thévenoux <>
Soumis le : jeudi 11 mai 2017 - 15:17:22
Dernière modification le : jeudi 15 juin 2017 - 09:09:23
Document(s) archivé(s) le : samedi 12 août 2017 - 13:37:21

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Claude-Pierre Jeannerod, Christophe Monat, Laurent Thévenoux. More accurate complex multiplication for embedded processors. 12th IEEE International Symposium on Industrial Embedded Systems (SIES 2017), Jun 2017, Toulouse, France. <https://sies2017.org/>. <hal-01512760v2>

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