Opportunities of CMOS-MEMS integration through LSI foundry and open facility

Abstract : Since the 2000s, several countries have established micro- and nanofabrication platforms for the research and education community as national projects. By combining such platforms with VLSI multichip foundry services, various integrated devices, referred to as“CMOS-MEMS”, can be realized without constructing an entire cleanroom. In this paper, we summarize MEMS-last postprocess schemes for CMOS devices on a bulk silicon wafer as well as on a silicon-on-insulator (SOI) wafer using an open-access cleanroom of the Nanotechnology Platform of MEXT Japan. The integration devices presented in this article are free-standing structures and postprocess isolated LSI devices. Postprocess issues are identified with their solutions, such as the reactive ion etching (RIE) lag for dry release and the impact of the deep RIE (DRIE) postprocess on transistor characteristics. Integration with nonsilicon materials is proposed as one of the future directions.
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Article dans une revue
Japanese Journal of Applied Physics, part 1 : Regular papers, Short Notes, 2017, 56 (06GA03), 〈http://iopscience.iop.org/1347-4065/56/6S1/06GA03〉. 〈10.7567/JJAP.56.06GA03〉
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https://hal.archives-ouvertes.fr/hal-01511015
Contributeur : Matthieu Denoual <>
Soumis le : jeudi 20 avril 2017 - 11:27:42
Dernière modification le : jeudi 13 septembre 2018 - 15:24:07

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Yoshio Mita, Eric Lebrasseur, Yuki Okamoto, Frédéric Marty, R. Setoguchi, et al.. Opportunities of CMOS-MEMS integration through LSI foundry and open facility. Japanese Journal of Applied Physics, part 1 : Regular papers, Short Notes, 2017, 56 (06GA03), 〈http://iopscience.iop.org/1347-4065/56/6S1/06GA03〉. 〈10.7567/JJAP.56.06GA03〉. 〈hal-01511015〉

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