Finite-Length Quasi-Synchronous LDPC Decoders

François Leduc-Primeau (1, 2) , Warren J. Gross (3)

1 Lab-STICC_TB_CACS_IAS
2 ELEC - Département Electronique
3 Department of Electrical and Computer Engineering [Montréal]

Quasi-synchronous systems aim to reduce energy consumption by allowing timing violations in a synchronous circuit, while performance guarantees are provided by analyzing the system with a suitable deviation model. This paper studies the performance of quasi-synchronous LDPC decoders for regular codes of finite length. We present an approach to accurately predict the decoding performance and energy consumption of the decoder for a specific average channel quality and maximum number of iterations. These analytical results are then compared with gate-level circuit simulations of a quasi-synchronous decoder.

Domaines: Electronique; Traitement du signal et de l'image [eess.SP]

François Leduc-Primeau, Warren J. Gross. Finite-Length Quasi-Synchronous LDPC Decoders. 9th International Symposium on turbo codes and iterative information processing (ISTC 2016), Sep 2016, Brest, France. pp.325-329, ⟨10.1109/ISTC.2016.7593130⟩. ⟨hal-01487083⟩