M. P. Lin, Y. Chang, and C. Hung, Recent research development and new challenges in analog layout synthesis, 2016 21st Asia and South Pacific Design Automation Conference (ASP-DAC), pp.617-622, 2016.
DOI : 10.1109/ASPDAC.2016.7428080

P. Lin, Y. Chang, and S. Lin, Analog Placement Based on Symmetry-Island Formulation, Computer-Aided Design of Integrated Circuits and Systems, pp.791-804, 2009.

S. Kirkpatrick, C. D. Gelatt, and M. P. Vecchi, Optimization by Simulated Annealing, Science New Series, vol.220, issue.4598, pp.671-680, 1983.
DOI : 10.1126/science.220.4598.671

URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=

R. Iskander, M. Louërat, and A. Kaiser, Hierarchical sizing and biasing of analog firm intellectual properties, Integration, the VLSI Journal, pp.172-188, 2013.
DOI : 10.1016/j.vlsi.2012.01.001

URL : https://hal.archives-ouvertes.fr/hal-01287767