On-line Testing for VLSI—A Compendium of Approaches - Archive ouverte HAL Accéder directement au contenu
Chapitre D'ouvrage Année : 1970

On-line Testing for VLSI—A Compendium of Approaches

Résumé

This paper presents an overview of a comprehensive collection of on-line testing techniques for VLSI. Such techniques are for instance: self-checking design, allowing high quality concurrent checking by means of hardware cost drastically lower than duplication; signature monitoring, allowing low cost concurrent error detection for FSMs; on-line monitoring of reliability relevant parameters such as current, temperature, abnormal delay, signal activity during steady state, radiation dose, clock waveforms, etc.; exploitation of standard BIST, or implementation of BIST techniques specific to on-line testing (Transparent BIST, Built-In Concurrent Self-Test, ...); exploitation of scan paths to transfer internal states for performing various tasks for on-line testing or fault tolerance; fail-safe techniques for VLSI, avoiding complex fail-safe interfaces using discrete components; radiation hardened designs, avoiding expensive fabrication process such as SOI, etc.

Dates et versions

hal-01478912 , version 1 (28-02-2017)

Licence

Paternité - Pas d'utilisation commerciale

Identifiants

Citer

M. Nicolaidis, Y. Zorian. On-line Testing for VLSI—A Compendium of Approaches. On-Line Testing for VLSI, springer pp.7-20, 1970, 978-1-4419-5033-8. ⟨10.1007/978-1-4757-6069-9_1⟩. ⟨hal-01478912⟩

Collections

UGA CNRS TIMA
98 Consultations
0 Téléchargements

Altmetric

Partager

Gmail Facebook X LinkedIn More