A 65nm CMOS Ramp Generator Design and its Application Towards a BIST Implementation of the Reduced-Code Static Linearity Test Technique for Pipeline ADCs

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https://hal.archives-ouvertes.fr/hal-01447813
Contributor : Haralampos Stratigopoulos <>
Submitted on : Friday, January 27, 2017 - 11:48:45 AM
Last modification on : Monday, June 10, 2019 - 6:08:06 PM

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Guillaume Renaud, Manuel Barragan, Asma Laraba, Haralampos-G. Stratigopoulos, Salvador Mir, et al.. A 65nm CMOS Ramp Generator Design and its Application Towards a BIST Implementation of the Reduced-Code Static Linearity Test Technique for Pipeline ADCs. Journal of Electronic Testing, Springer Verlag, 2016, ⟨10.1007/s10836-016-5599-8⟩. ⟨hal-01447813⟩

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