I/O contention aware mapping of multi-criticalities real-time applications over many-core architectures

Laure Abdallah (1) , Mathieu Jan (1) , Jérôme Ermont (2, 3) , Christian Fraboul (2)

1 LIST (CEA) - Laboratoire d'Intégration des Systèmes et des Technologies
2 IRIT-RMESS - Réseaux, Mobiles, Embarqués, Sans fil, Satellites
3 Toulouse INP - Institut National Polytechnique (Toulouse)

Many-core architectures are more promising hardware to design real-time systems than multi-core systems as they should enable an easier mastered integration of a higher number of applications, potentially of different level of criticalities. However, the worst-case behavior of the Network-on-Chip (NoC) for both inter-core and core-to-Input/Output1 (I/O) communications of critical applications must be established. The mapping over the NoC of both critical and non-critical applications has an impact on the network contention these critical communications exhibit. So far, all existing mapping strategies have focused on inter-core communications. However, many-cores in embedded real-time systems can be integrated within backbone Ethernet networks, as they mostly provide Ethernet controllers as I/O interfaces. In this work, we first show that Ethernet packets can be dropped due to an internal congestion in the NoC, if these coreto I/O communications are not taken into account while mapping applications. To solve this issue, we show on an avionic case study the benefits of the core-to-I/O contention-aware mapping strategy we propose.

Mots clés: Embedded technology

Domaines: Réseaux et télécommunications [cs.NI]; Système d'exploitation [cs.OS]; Architectures Matérielles [cs.AR]; Systèmes embarqués

Laure Abdallah, Mathieu Jan, Jérôme Ermont, Christian Fraboul. I/O contention aware mapping of multi-criticalities real-time applications over many-core architectures. 22nd IEEE Real-Time and embedded Technology and Applications symposium (RTAS 2016), Apr 2016, Vienna, Austria. pp. 25-28. ⟨hal-01445139⟩