A Low-Cost Reliability vs. Cost Trade-Off Methodology to Selectively Harden Logic Circuits

Imran Wali (1) , Bastien Deveautour (1) , Arnaud Virazel (1) , Alberto Bosio (1) , Patrick Girard (1) , Matteo Sonza Reorda (2)

1 SysMIC - Conception et Test de Systèmes MICroélectroniques
2 DET - Dipartimento di Elettronica e Telecomunicazioni [Torino]

Selecting the ideal trade-off between reliability and cost associated with a fault tolerant architecture generally involves an extensive design space exploration. Employing state-of-the-art susceptibility estimation methods makes it unscalable with design complexity. In this paper we introduce a low-cost susceptibility analysis methodology that helps identifying the most vulnerable circuit elements for hardening with less computational effort and orders of magnitude faster. Our experimental results show that the methodology offers huge gain in terms of computational effort (2,500× faster) in comparison with a fault-injection based method and produces results within acceptable degree of accuracy.

Mots clés: High dependability; Fault tolerance; Fault injection; Susceptibility analysis; Single event transient; Permanent fault; Delay fault; Power consumption

Domaines: Electronique

Imran Wali, Bastien Deveautour, Arnaud Virazel, Alberto Bosio, Patrick Girard, et al.. A Low-Cost Reliability vs. Cost Trade-Off Methodology to Selectively Harden Logic Circuits. ETS: European Test Symposium, May 2016, Amsterdam, Netherlands. ⟨10.1109/ETS.2016.7519296⟩. ⟨hal-01444734⟩