Service interruption on Monday 11 July from 12:30 to 13:00: all the sites of the CCSD (HAL, EpiSciences, SciencesConf, AureHAL) will be inaccessible (network hardware connection).
Skip to Main content Skip to Navigation
Conference papers

Capacitor based SneakPath compensation circuit for transistor-less ReRAM architectures

Abstract : With the arrival of crosspoint based memories on the consumer market, high-density resistive memories could be introduced as flash memories replacement or as storage class memory. However, transistor-Less Resistive memory architectures using 1Selector-1resistance bitcells suffer from performances loss due to sneaking current through unselected bitcells. Beyond the back end of line selector design, circuit design solutions have to be pushed in order to improve precision during programming steps. In this paper we propose a novel capacitor based 2-steps SneakPath compensation circuit for transistor-less architectures of resistive memories. Compared to standard SneakPath compensation circuits, it ensures up to 20x of area improvement and more than 3x reduction of the variability effects for a 28nm CMOS node.
Complete list of metadata
Contributor : IM2NP Bibliométrie Connect in order to contact the contributor
Submitted on : Friday, January 13, 2017 - 4:02:14 PM
Last modification on : Wednesday, November 3, 2021 - 7:28:56 AM




Alexandre Levisse, Bastien Giraud, Jean-Philippe Noel, Mathieu Moreau, Jean-Michel Portal. Capacitor based SneakPath compensation circuit for transistor-less ReRAM architectures. Proceedings of the 2016 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH), Jul 2016, Beijing, China. pp.7-12, ⟨10.1145/2950067.2950073⟩. ⟨hal-01435118⟩



Record views