Hierarchical FPGA clustering to improve routability

Zied Marrakchi 1 Hayder Mrabet 1 Habib Mehrez 1
1 CIAN - Circuits Intégrés Numériques et Analogiques
LIP6 - Laboratoire d'Informatique de Paris 6
Abstract : In this paper we present a new clustering technique, based on the multilevel partitioning, for hierarchical FPGAs. The purpose of this technique is to reduce area and power by considering routability in early steps of the CAD flow. We show that this technique can reduce the needed tracks in the routing step by 15% compared with the other packing tools.
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Conference papers
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https://hal.archives-ouvertes.fr/hal-01419664
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Submitted on : Monday, December 19, 2016 - 5:28:10 PM
Last modification on : Thursday, March 21, 2019 - 2:31:30 PM

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Zied Marrakchi, Hayder Mrabet, Habib Mehrez. Hierarchical FPGA clustering to improve routability. PRIME 2005 - IEEE Conference on Ph.D. Research in MicroElectronics and Electronics, Jul 2005, Lausanne, Switzerland. pp.165-168, ⟨10.1109/RME.2005.1543029⟩. ⟨hal-01419664⟩

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