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A Flexible SoC and Its Methodology for Parser-Based Applications

Abstract : Embedded systems are being increasingly network interconnected. They require to interact with their environment through text-based protocol messages. Parsing such messages is control-dominated. The work presented in this article attempts to accelerate message parsers using a codesign-based approach. We propose a generic architecture associated to an automated design methodology that enables a SoC/SoPC system generation from high-level specifications of message protocols. Experimental results obtained on a Xilinx ML605 board show acceleration factors ranging from 4 to 11. Both static and dynamic reconfigurations of coprocessors are discussed then evaluated so as to reduce the system hardware complexity.
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Contributor : Laurent Réveillère <>
Submitted on : Tuesday, December 13, 2016 - 2:04:25 PM
Last modification on : Friday, July 10, 2020 - 4:10:29 PM
Long-term archiving on: : Tuesday, March 14, 2017 - 1:10:54 PM


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Bertrand Le Gal, Yérom-David Bromberg, Laurent Réveillère, Jigar Solanki. A Flexible SoC and Its Methodology for Parser-Based Applications. ACM Transactions on Reconfigurable Technology and Systems (TRETS), ACM, 2016, 10 (1), pp.4. ⟨10.1145/2939379⟩. ⟨hal-01415653⟩



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