Implementation and Validation of a Low-Cost Single-Event Latchup Mitigation Scheme

M. Nicolaidis (1) , K. Torki (1) , F. Natali (2) , K. Belhaddad (2) , D. Alexandrescu (2)

1 TIMA - Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés
2 IROC TECHNOLOGIES - iROc Technologies

We present the principles, implementation, validation, and evaluation results of a low-cost si ngle- event-latchup design mitigation scheme for memories.

Domaines: Micro et nanotechnologies/Microélectronique

M. Nicolaidis, K. Torki, F. Natali, K. Belhaddad, D. Alexandrescu. Implementation and Validation of a Low-Cost Single-Event Latchup Mitigation Scheme. 5th IEEE Workshop on Silicon Errors in Logic - System Effects (SELSE’09), Mar 2009, Stanford, Ca., United States. ⟨hal-01413151⟩