SET-Factor: An Analysis and Design Tool to Reduce SET Sensitivity in Integrated Circuits

C. Lazzari (1) , T. Assis (2) , F. Kastensmidt (1) , G. Wirth (2) , Lorena Anghel (3) , Ricardo Reis (1)

1 DELET
2 Vanderbilt University [Nashville]
3 TIMA - Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés

Domaines: Micro et nanotechnologies/Microélectronique

C. Lazzari, T. Assis, F. Kastensmidt, G. Wirth, Lorena Anghel, et al.. SET-Factor: An Analysis and Design Tool to Reduce SET Sensitivity in Integrated Circuits. 13th IEEE European Test Symposium (ETS'08), May 2008, Verbania, Italy. ⟨hal-01408791⟩