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Article Dans Une Revue IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Année : 2016

Formal Verification of Arithmetic Circuits by Function Extraction

Cunxi Yu
  • Fonction : Auteur
Walter Brown
  • Fonction : Auteur
Duo Liu
  • Fonction : Auteur
Maciej Ciesielski
  • Fonction : Auteur

Résumé

The paper presents an algebraic approach to functional verification of gate-level, integer arithmetic circuits. It is based on extracting a unique bit-level polynomial function computed by the circuit directly from its gate-level implementation. The method can be used to verify the arithmetic function computed by the circuit against its known specification, or to extract an arithmetic function implemented by the circuit. Experiments were performed on arithmetic circuits synthesized and mapped onto standard cells using ABC system. The results demonstrate scalability of the method to large arithmetic circuits, such as multipliers, multiply-accumulate, and other elements of arithmetic datapaths with up to 512-bit operands and over 2 million gates. The results show that our approach wins over the state-of-the-art SAT/SMT solvers by several orders of magnitude of CPU time. The procedure has linear runtime and memory complexity, measured by the number of logic gates.

Dates et versions

hal-01404976 , version 1 (29-11-2016)

Identifiants

Citer

Cunxi Yu, Walter Brown, Duo Liu, André Rossi, Maciej Ciesielski. Formal Verification of Arithmetic Circuits by Function Extraction. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2016, 35 (12), pp.2131-2142. ⟨10.1109/TCAD.2016.2547898⟩. ⟨hal-01404976⟩

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