A time driven adder generator architecture

Abstract : This paper presents the design and implementation of a time driven adder generator architecture. There exists a large variety of adders designed to satisfy different computation requirements, in particular we list the Carry Look Ahead (CLA) adder, the skip adder, the ripple adder, the carry select adder (CSA), etc. These different architectures will offer different delays and it is up to the user to chose among them. The design we present here allows the parametrization of the architecture to fit ones design constraints. From the word length and the wanted delay the generator outputs a suitable architecture.
Complete list of metadatas

https://hal.archives-ouvertes.fr/hal-01396484
Contributor : Lucie Torella <>
Submitted on : Monday, November 14, 2016 - 2:57:19 PM
Last modification on : Thursday, March 21, 2019 - 1:03:56 PM

Licence


Distributed under a Creative Commons Attribution - NonCommercial 4.0 International License

Links full text

Identifiers

Citation

Mourad Aberbour, Alain Houelle, Habib Mehrez, Nicolas Vaucher, Alain Guyot. A time driven adder generator architecture. 9th IFIP International Conference on Very Large Scale Integration (VLSI'97), Aug 1997, Gramado, RS, Brazil. pp.453-463, ⟨10.1007/978-0-387-35311-1_37⟩. ⟨hal-01396484⟩

Share

Metrics

Record views

123