Including testability in a high-level synthesis environment

A. Ribeiro Antunes (1) , V. Castro Alves (2) , A. Mesquita (1) , M. Marzouki (2)

1 UFRJ - Universidade Federal do Rio de Janeiro [Brasil] = Federal University of Rio de Janeiro [Brazil] = Université fédérale de Rio de Janeiro [Brésil]
2 TIMA - Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés

This paper presents a methodology to synthesize testable circuits in a High-Level Synthesis environment using a graph-based approach. The complexity of the algorithm involved in the proposed approach is of the order O(N), where N is the number of vertices and edges in the graph.

Domaines: Micro et nanotechnologies/Microélectronique

A. Ribeiro Antunes, V. Castro Alves, A. Mesquita, M. Marzouki. Including testability in a high-level synthesis environment. 1st IEEE International High Level Design Validation and Test Workshop (HLDVT'96), Nov 1996, Oakland, California, United States. ⟨hal-01396387⟩