Guidelines on 3D VLSI design regarding the intermediate BEOL process influence

A. Ayres (1) , O. Rozeau (1) , B. Borot (2) , Laurent Fesquet (3) , G. Cibrario (1) , P. Batude (1) , M. Vinet (1)

1 CEA-LETI - Commissariat à l'énergie atomique et aux énergies alternatives - Laboratoire d'Electronique et de Technologie de l'Information
2 ST-CROLLES - STMicroelectronics [Crolles]
3 TIMA - Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés

This paper aims at identifying the critical parameters for intermediate back end of line (BEOL) in 3DVLSI in order to benefit from higher circuit gain in performance. Thanks to circuit simulations in a 3D environment PDK, the capacitance is identified as the most critical parameter for IC performance of circuits using two intermetal levels. The critical wirelength upon which a gain in performance is obtained by the 3D stacking is evaluated as a function of BEOL flavor.

Domaines: Micro et nanotechnologies/Microélectronique

A. Ayres, O. Rozeau, B. Borot, Laurent Fesquet, G. Cibrario, et al.. Guidelines on 3D VLSI design regarding the intermediate BEOL process influence. IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), Oct 2015, Sonoma Valley, CA, United States. pp.1-2. ⟨hal-01393435⟩