Pre-sorted Forward-Backward NB-LDPC Check Node Architecture

Hassan Harb (1, 2) , Cédric Marchand (1) , Laura Conde-Canencia (1) , Emmanuel Boutillon (1) , Ali Al Ghouwayel (2)

1 Lab-STICC_UBS_CACS_IAS
2 LIU - Lebanese International University

This paper deals with reduced-complexity NB-LDPC check node implementation based on the Extended Min-Sum algorithm. We propose to apply a recently introduced pre-sorting technique to the forward-backward architecture. The pre-sorting of the check node inputs allows for significant complexity reduction. Simulation and synthesis results showed that this approach does not introduce any performance loss and can lead to significant area reduction in FPGA implementations (up to 54% for high check node degrees).

Mots clés: NB-LDPC; Check Node; Forward-backward

Domaines: Electronique

Hassan Harb, Cédric Marchand, Laura Conde-Canencia, Emmanuel Boutillon, Ali Al Ghouwayel. Pre-sorted Forward-Backward NB-LDPC Check Node Architecture. IEEE International Workshop on Signal Processing Systems (SIPS'2016), Oct 2016, Dallas, United States. ⟨hal-01390916⟩