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VLS Grown 4H-SiC Buried P+ Layers for JFET Lateral Structures

Abstract : Lateral JFET transistors have been fabricated with N and P-type channels tentatively integrated monolithically on the same SiC wafer. Buried P+ SiC layers grown by Vapor-Liquid-Solid (VLS) selective epitaxy were utilized as source and drain for the P-JFET and as gate for the N-JFET. The ohmicity of the contacts, both on VLS grown P+ and ion implanted N+ layers, has been confirmed by Transfer Length Method (TLM) measurements. A premature leakage current is observed on the P/N junction created directly by the P+ VLS gate layer, probably due to imperfect VLS (P+) / CVD (N+) SiC interface.
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Submitted on : Monday, May 6, 2019 - 10:14:01 AM
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Selsabil Sejil, Farah Laariedh, Mihai Lazar, Davy Carole, Christian Brylinski, et al.. VLS Grown 4H-SiC Buried P+ Layers for JFET Lateral Structures. Materials Science Forum, Trans Tech Publications Inc., 2015, 821-823, pp.789 - 792. ⟨10.4028/www.scientific.net/MSF.821-823.789⟩. ⟨hal-01387983⟩

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