P. Bessière, C. Laugier, and R. Siegwart, Probabilistic Reasoning and Decision Making in Sensory-Motor Systems, 2008.
DOI : 10.1007/978-3-540-79007-5

W. J. Ma, J. M. Beck, P. E. Latham, and A. Pouget, Bayesian inference with probabilistic population codes, Nature Neuroscience, vol.9, issue.11, pp.1432-1438, 2006.
DOI : 10.1038/nn1691

J. Laurens and J. Droulez, Bayesian processing of vestibular information, Biological Cybernetics, vol.86, issue.3, pp.389-404, 2007.
DOI : 10.1007/s00422-006-0133-1

A. Houillon, P. Bessière, and J. Droulez, The Probabilistic Cell: Implementation of a Probabilistic Inference by the Biochemical Mechanisms of Phototransduction, Acta Biotheoretica, vol.10, issue.2, pp.103-120, 2010.
DOI : 10.1007/s10441-010-9104-y
URL : https://hal.archives-ouvertes.fr/hal-00540300

O. Lebeltel, P. Bessière, J. Diard, and E. Mazer, Bayesian Robot Programming, Autonomous Robots, vol.16, issue.1, pp.49-79, 2004.
DOI : 10.1023/B:AURO.0000008671.38949.43
URL : https://hal.archives-ouvertes.fr/inria-00189723

K. Bernstein, R. K. Cavin, W. Porod, A. Seabaugh, and J. Welser, Device and Architecture Outlook for Beyond CMOS Switches, Proc. IEEE, pp.2169-2184, 2010.
DOI : 10.1109/JPROC.2010.2066530
URL : http://mediatum.ub.tum.de/doc/1273195/document.pdf

I. Pournara, C. Bouganis, and G. A. Constantinides, FPGAaccelerated Bayesian learning for reconstruction of gene regulatory networks, Proc. Int. Conf. Field Program. Logic Appl. (FPL), pp.323-328, 2005.

M. Lin, I. Lebedev, and J. Wawrzynek, High-throughput bayesian computing machine with reconfigurable hardware, Proceedings of the 18th annual ACM/SIGDA international symposium on Field programmable gate arrays, FPGA '10
DOI : 10.1145/1723112.1723127

A. Int, Symp. Field Program. Gate Arrays, pp.73-82, 2010.

B. Vigoda, Analog logic: Continuous-time analog circuits for statistical signal processing, Ph.D. dissertation, Program Media Arts Sci., School Archit. Plan. Massachusetts Institute of Technology, 2003.

P. Mroszczyk and P. Dudek, The accuracy and scalability of continuoustime Bayesian inference in analogue CMOS circuits, Proc. ISCAS, pp.1576-1579, 2014.

J. and V. Neumann, Probabilistic Logics and the Synthesis of Reliable Organisms From Unreliable Components, 1956.
DOI : 10.1515/9781400882618-003

B. Gaines, Stochastic Computing Systems, Advances in Information Systems Science, pp.37-172, 1969.
DOI : 10.1007/978-1-4899-5841-9_2

V. Gaudet and A. Rapley, Iterative decoding using stochastic computation, Electronics Letters, vol.39, issue.3, pp.299-301, 2003.
DOI : 10.1049/el:20030217

C. Winstead and S. Howard, A Probabilistic LDPC-Coded Fault Compensation Technique for Reliable Nanoscale Computing, IEEE Transactions on Circuits and Systems II: Express Briefs, vol.56, issue.6, pp.484-488, 2009.
DOI : 10.1109/TCSII.2009.2020946

S. Gaba, P. Sheridan, J. Zhou, S. Choi, and W. Lu, Stochastic memristive devices for computing and neuromorphic applications, Nanoscale, vol.22, issue.1, pp.5872-5878, 2013.
DOI : 10.1039/c3nr01176c

P. Knag, W. Lu, and Z. Zhang, A Native Stochastic Computing Architecture Enabled by Memristors, IEEE Transactions on Nanotechnology, vol.13, issue.2, pp.283-293, 2014.
DOI : 10.1109/TNANO.2014.2300342

D. Querlioz, O. Bichler, A. F. Vincent, and C. Gamrat, Bioinspired Programming of Memory Devices for Implementing an Inference Engine, Proc. IEEE, pp.1398-1416, 2015.
DOI : 10.1109/JPROC.2015.2437616

T. Hamilton, S. Afshar, A. Van-schaik, and J. Tapson, Stochastic Electronics: A Neuro-Inspired Design Paradigm for Integrated Circuits, Proc. IEEE, pp.843-859, 2014.
DOI : 10.1109/JPROC.2014.2310713

A. Fukushima, T. Seki, K. Yakushiji, H. Kubota, H. Imamura et al., Spin dice: A scalable truly random number generator based on spintronics, Applied Physics Express, vol.7, issue.8, 2014.
DOI : 10.7567/APEX.7.083001

W. H. Choi, Y. Lv, J. Kim, A. Deshpande, G. Kang et al., A magnetic tunnel junction based true random number generator with conditional perturb and real-time output probability tracking, Proc. IEDM, pp.315-318, 2014.

D. E. Muller, Theory of Asynchronous Circuits, Internal Report, issue.66, 1955.

M. Shams, J. C. Ebergen, and M. I. Elmasry, Modeling and comparing CMOS implementations of the C-element, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol.6, issue.4, pp.563-567, 1998.
DOI : 10.1109/92.736128

C. Winstead, C-element multiplexing for fault-tolerant logic circuits, Electronics Letters, vol.45, issue.19, pp.969-970, 2009.
DOI : 10.1049/el.2009.1073

S. Sharifi-tehrani, C. Winstead, W. J. Gross, S. Mannor, S. L. Howard et al., Relaxation Dynamics in Stochastic Iterative Decoders, IEEE Transactions on Signal Processing, vol.58, issue.11, pp.5955-5961, 2010.
DOI : 10.1109/TSP.2010.2066269

A. F. Vincent, J. Larroque, W. S. Zhao, N. Ben-romdhane, O. Bichler et al., Spin-Transfer Torque Magnetic Memory as a Stochastic Memristive Synapse for Neuromorphic Systems, IEEE Transactions on Biomedical Circuits and Systems, vol.9, issue.2, pp.166-174, 2015.
DOI : 10.1109/TBCAS.2015.2414423

J. A. Brzozowski and K. Raahemifar, Testing C-elements is not elementary, Proceedings Second Working Conference on Asynchronous Design Methodologies, pp.150-159, 1995.
DOI : 10.1109/WCADM.1995.514652

G. Tziantzioulis, A. M. Gok, S. M. Faisal, N. Hardavellas, S. Memik et al., b-HiVE, Proceedings of the 52nd Annual Design Automation Conference on, DAC '15, 2015.
DOI : 10.1145/2744769.2744805