Digital Reconstruction Stage Implementation of FBD Sigma Delta ADC for SDR Receiver
Résumé
This paper presents a fixed point implementation of a digital reconstruction stage in frequency band decomposition (FBD) Sigma Delta analog-to-digital converter (ADC) which is intended for software defined radio (SDR) multistandard receiver. The implemented architecture is composed of 3 parallel branches for the UMTS use case. The digital reconstruction stage is essentially composed of digital finite impulse response (FIR) filters. In addition, the frequency conversions performed in the digital reconstruction stage are ensured by digital oscillators which are carefully tuned to obtain the required frequencies and phases. These oscillators are dedicated to demodulation and modulation operations. The proposed architecture is digitally implemented on a field programmable gate array (FPGA) target. Then, it is tested thanks to FPGA-in- the-loop (FIL) tool using MATLAB/SIMULINK interface. It allows us to compare our system to the simulation results that are done with MATLAB/SIMULINK in floating point.