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Conference papers

Power/Area trade-offs in 1-of-M parallel-prefix asynchronous adders

Résumé : This work describes generalized structures to design 1-of-M QDI (Quasi Delay-Insensitive) asynchronous adders. Those structures allow to design from simple ripple-carry adders to faster parallel-prefix adders. The proposed method is fully automated and integrated in TAST (TIMA Asynchronous Synthesis Tool) tools suite. This paper also demonstrates that the most widely used dual-rail encoding (binary representation in QDI circuits) is not the best solution for numbers’ representation in asynchronous circuits. In fact, according to the domain of values to be represented increasing the radix leads to parallel-prefix adders with lower area, delay and power consumption. Hence, this work enables the designer to optimize his/her design by choosing the appropriate 1-of-M number representation.
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Contributor : Lucie Torella Connect in order to contact the contributor
Submitted on : Wednesday, October 5, 2016 - 3:05:32 PM
Last modification on : Friday, December 11, 2020 - 8:28:05 AM


Distributed under a Creative Commons Attribution - NonCommercial 4.0 International License


  • HAL Id : hal-01376723, version 1




J. Fragoso, G. Sicard, Marc Renaudin. Power/Area trade-offs in 1-of-M parallel-prefix asynchronous adders. 13th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS'03), Sep 2003, Torino, Italie. pp.171-180. ⟨hal-01376723⟩



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