Power/Area trade-offs in 1-of-M parallel-prefix asynchronous adders

J. Fragoso (1) , G. Sicard (1) , Marc Renaudin (1)

1 TIMA - Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés

This work describes generalized structures to design 1-of-M QDI (Quasi Delay-Insensitive) asynchronous adders. Those structures allow to design from simple ripple-carry adders to faster parallel-prefix adders. The proposed method is fully automated and integrated in TAST (TIMA Asynchronous Synthesis Tool) tools suite. This paper also demonstrates that the most widely used dual-rail encoding (binary representation in QDI circuits) is not the best solution for numbers’ representation in asynchronous circuits. In fact, according to the domain of values to be represented increasing the radix leads to parallel-prefix adders with lower area, delay and power consumption. Hence, this work enables the designer to optimize his/her design by choosing the appropriate 1-of-M number representation.

Domaines: Micro et nanotechnologies/Microélectronique

J. Fragoso, G. Sicard, Marc Renaudin. Power/Area trade-offs in 1-of-M parallel-prefix asynchronous adders. 13th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS'03), Sep 2003, Torino, Italie. pp.171-180. ⟨hal-01376723⟩