A framework for VHDL combining theorem proving and symbolic simulation

P. Georgelin (1) , P. Ostier (1) , D. Borrione (1)

1 TIMA - Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés

We present the status of an on-going work aiming at introducing symbolic simulation and theorem proving in a design flow that uses conventional description and simulation languages. This paper focuses on the formalization of the cycle simulation semantics of a synchronous subset of VHDL, in the ACL2 logic. The model is executable, and the results of its symbolic simulation can be proven equal to a specified expression.The ACL2 input is produced automatically from the VHDL source, which relieves the designer from an error prone manual translation.

Domaines: Micro et nanotechnologies/Microélectronique

P. Georgelin, P. Ostier, D. Borrione. A framework for VHDL combining theorem proving and symbolic simulation. Third International Workshop on the ACL2 Theorem Prover and its Applications (ACL2'02), Apr 2002, Grenoble, France. pp.1-15. ⟨hal-01375425⟩