High-level synthesis of multiple word-length DSP algorithms using heterogeneousresource FPGAs, Field Programmable Logic and Applications, pp.1-4, 2006. ,
Table-Based Division by Small Integer Constants, pp.53-63 ,
DOI : 10.1049/ip-cdt:19941414
URL : https://hal.archives-ouvertes.fr/ensl-00642145
Floating-Point Exponentiation Units for Reconfigurable Computing, ACM Transactions on Reconfigurable Technology and Systems, vol.6, issue.1, pp.1-4, 2013. ,
DOI : 10.1145/2457443.2457447
URL : https://hal.archives-ouvertes.fr/ensl-00718637
High-Performance Computing Using FPGAs, chapter Reconfigurable Arithmetic for High-Performance Computing, pp.631-663 ,
An FPGA-specific approach to floating-point accumulation and sum-of-products, 2008 International Conference on Field-Programmable Technology, pp.33-40, 2008. ,
DOI : 10.1109/FPT.2008.4762363
URL : https://hal.archives-ouvertes.fr/ensl-00268348
Polly's polyhedral scheduling in the presence of reductions, International Workshop on Polyhedral Compilation Techniques, 2015. ,
GeCoS: A framework for prototyping custom hardware design flows, Source Code Analysis and Manipulation, pp.100-105, 2013. ,
Range and bitmask analysis for hardware optimization in high-level synthesis, 2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC), pp.773-779, 2013. ,
DOI : 10.1109/ASPDAC.2013.6509694
Floating-point design with vivado HLS, 2012. Xilinx Application Note ,
Accurate parallel floating-point accumulation, IEEE Transactions on Computers, pp.3224-3238, 2016. ,
DOI : 10.1109/arith.2013.19
URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.366.2009
Optimistic Parallelization of Floating-Point Accumulation, 18th IEEE Symposium on Computer Arithmetic (ARITH '07), pp.205-216, 2007. ,
DOI : 10.1109/ARITH.2007.25
URL : http://authors.library.caltech.edu/20099/1/Kapre2007p907318Th_Ieee_Symposium_On_Computer_Arithmetic_Proceedings.pdf
The exact dot product as basic tool for long interval arithmetic. Computing, pp.307-313, 2011. ,
FPGA Floating Point Datapath Compiler, 2009 17th IEEE Symposium on Field Programmable Custom Computing Machines, pp.259-262, 2009. ,
DOI : 10.1109/FCCM.2009.54
Accelerating pipelined integer and floatingpoint accumulations in configurable hardware with delayed addition techniques, IEEE Transactions on Computers, pp.208-218, 2000. ,
DOI : 10.1109/12.841125
Handbook of Floating-Point Arithmetic, 2010. ,
DOI : 10.1007/978-0-8176-4705-6
URL : https://hal.archives-ouvertes.fr/ensl-00379167
A survey and evaluation of fpga high-level synthesis tools. Computer-Aided Design of Integrated Circuits and Systems, pp.1591-1604, 2016. ,
Detection of scans in the polytope model. Parallel Algorithms and Applictations, pp.229-263, 2000. ,
Automatic Fixed- Point Conversion: a Gateway to High-Level Power Optimization, Design Automation and Test in Europe, 2014. ,
URL : https://hal.archives-ouvertes.fr/hal-01100230
MixFX-SCORE: Heterogeneous Fixed-Point Compilation of Dataflow Computations, 2014 IEEE 22nd Annual International Symposium on Field-Programmable Custom Computing Machines, pp.206-209, 2014. ,
DOI : 10.1109/FCCM.2014.64