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Comparison of topside contact layouts for power dies embedded in PCB

Abstract : Embedding of power semiconductor dies in PCB is a very attractive technology, especially to achieve interconnects with a very low parasitic inductance and resistance. In this paper, we focus on the contact resistance and current distribution in a large (6×6mm 2) diode embedded in PCB, as a function of the layout of its topside contact. We demonstrate that by choosing a suitable contact layout, it is possible to achieve a very low contact resistance.
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https://hal.archives-ouvertes.fr/hal-01373042
Contributor : Cyril Buttay <>
Submitted on : Wednesday, September 28, 2016 - 10:13:00 AM
Last modification on : Thursday, April 1, 2021 - 3:35:39 AM
Long-term archiving on: : Thursday, December 29, 2016 - 12:23:34 PM

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Chenjiang Yu, Cyril Buttay, Eric Labouré, Vincent Bley, Céline Combettes, et al.. Comparison of topside contact layouts for power dies embedded in PCB. ESTC, IMAPS, Sep 2016, Grenoble, France. ⟨10.1109/ESTC.2016.7764707⟩. ⟨hal-01373042⟩

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