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A System-On-A-Chip for Pattern Recognition Architecture and Design Methodology

Abstract : We address in this paper the design and specification of a heterogeneous architecture of a SOC (System-On-a-Chip) for pattern recognition. Once the algorithms involved presented, we investigate the hardware/software codesign methodology, the system architecture and finally the VLSI physical integration. We conclude by giving results on the performance of the system regarding recognition rate and VLSI characteristics.
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Contributor : Habib MEHREZ Connect in order to contact the contributor
Submitted on : Tuesday, September 27, 2016 - 4:46:49 PM
Last modification on : Sunday, June 26, 2022 - 10:00:20 AM




Mourad Aberbour, Habib Mehrez, François Durbin, Jacques Haussy, P. Lalande, et al.. A System-On-A-Chip for Pattern Recognition Architecture and Design Methodology. CAMP 2000 - Fifth International Workshop on Computer Architectures for Machine Perception, Sep 2000, Padova, Italy. pp.155--162, ⟨10.1109/CAMP.2000.875973⟩. ⟨hal-01372840⟩



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