A System-On-A-Chip for Pattern Recognition Architecture and Design Methodology

Abstract : We address in this paper the design and specification of a heterogeneous architecture of a SOC (System-On-a-Chip) for pattern recognition. Once the algorithms involved presented, we investigate the hardware/software codesign methodology, the system architecture and finally the VLSI physical integration. We conclude by giving results on the performance of the system regarding recognition rate and VLSI characteristics.
Document type :
Conference papers
Complete list of metadatas

https://hal.archives-ouvertes.fr/hal-01372840
Contributor : Habib Mehrez <>
Submitted on : Tuesday, September 27, 2016 - 4:46:49 PM
Last modification on : Thursday, March 21, 2019 - 2:31:38 PM

Identifiers

Citation

Mourad Aberbour, Habib Mehrez, François Durbin, Jacques Haussy, P. Lalande, et al.. A System-On-A-Chip for Pattern Recognition Architecture and Design Methodology. CAMP 2000 - Fifth International Workshop on Computer Architectures for Machine Perception, Sep 2000, Padova, Italy. pp.155--162, ⟨10.1109/CAMP.2000.875973⟩. ⟨hal-01372840⟩

Share

Metrics

Record views

96