Controlled placement and routing techniques to improve timing balance of WDDL designs in Mesh-based FPGA

Emna Amouri 1 Zied Marrakchi 1 Habib Mehrez 1
1 CIAN - Circuits Intégrés Numériques et Analogiques
LIP6 - Laboratoire d'Informatique de Paris 6
Abstract : The Wave Dynamic Differential Logic (WDDL) offers an affective way to address Differential Power Attack (DPA). However, the effectiveness of this countermeasure is guaranteed provided the routing of both the real and complementary paths is balanced, to obtain equal propagation delays and power consumption on differential signals.
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Conference papers
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https://hal.archives-ouvertes.fr/hal-01372837
Contributor : Habib Mehrez <>
Submitted on : Tuesday, September 27, 2016 - 4:46:43 PM
Last modification on : Thursday, March 21, 2019 - 2:31:34 PM

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Emna Amouri, Zied Marrakchi, Habib Mehrez. Controlled placement and routing techniques to improve timing balance of WDDL designs in Mesh-based FPGA. APCCAS 2010 - IEEE Asia Pacific Conference on Circuits and Systems, Dec 2010, Kuala Lumpur, Malaysia. pp.296--299, ⟨10.1109/APCCAS.2010.5774878⟩. ⟨hal-01372837⟩

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