Ouessant: Microcontroller approach for flexible accelerator integration and control in System-On-Chip

Pierre-Henri Horrein 1, 2 Benoît Porteboeuf 3 André Lalevee 4, 2, 5
Lab-STICC - Laboratoire des sciences et techniques de l'information, de la communication et de la connaissance
4 ADOPNET - Advanced technologies for operated networks
IRISA-D2 - RÉSEAUX, TÉLÉCOMMUNICATION ET SERVICES, Télécom Bretagne, UR1 - Université de Rennes 1
Abstract : When designing hardware accelerators for System on Chips, hardware and software integration can quickly become difficult. Heterogeneity in the interfaces prevents developers from efficiently using available hardware. In this paper, we propose an improved microcontroller approach to Intellectual Property (IP) core integration in System on Chips. This approach is based on an instruction set designed to control communications and execution of integrated IP. It provides memory access offloading, platform independent integration, and dynamic (i.e runtime controllable) pipelining between integrated IPs. As a result, it provides flexibility and simple access to hardware acceleration, with very low overhead. This approach has been validated on a real channel simulation application. Software integration of the approach is available for Linux or baremetal systems. The source code for the proposed solution is freely (as in Free Software) available, in order to benefit the community.
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Contributor : Bibliothèque Télécom Bretagne <>
Submitted on : Wednesday, September 21, 2016 - 7:02:15 PM
Last modification on : Wednesday, March 6, 2019 - 3:09:00 PM


  • HAL Id : hal-01370056, version 1


Pierre-Henri Horrein, Benoît Porteboeuf, André Lalevee. Ouessant: Microcontroller approach for flexible accelerator integration and control in System-On-Chip. FPL 2016 : 26th International Conference on Field-Programmable Logic and Applications, Aug 2016, Lausanne, Switzerland. ⟨hal-01370056⟩



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